1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to clocking of memory devices.
2. Description of the Related Art
A large memory capacity can be obtained for a memory system using a plurality of memory chips that are connected in a parallel architecture. For example, a memory system having an X32 data input/output bandwidth can use one DRAM that inputs/outputs 32-bit data in parallel through 32 data pins. To increase the memory capacity, the memory system can use two DRAMs on opposite sides of a memory board, and each DRAM can be accessed in an X16 mode.
FIG. 1 illustrates a conventional memory system. Referring to FIG. 1, a first memory chip 120 and a second memory chip 130 are respectively placed on the top and bottom of the board 110 in the memory system 100. The combination of the first memory chip 120 and the second memory chip 130 together support an X32 mode, and are installed horizontally along the X-axis of the board 110 in a mirroring scheme. In order to support the X32 mode in the memory system 100, 16-bit data input/output lines DQ are connected to the first memory chip 120 and 16-bit data input/output lines DQ are connected to the second memory chip 130. The structure of the data input/output lines is to provide each data input/output line DQ with the load of the memory chip 120 or 130 since signal integrity decreases if the load of the two memory chips 120 and 130 is applied on each data input/output line if 32-bit data input/output lines DQ are connected to the first memory chip 120 and the second memory chip 130.
As shown in FIGS. 2A-B, 32 data input/output pins DQ0 through DQ31 in the first memory chip 120 are connected to corresponding data transmitting clocks WCK01 and WCK23 which control timing of data input/output operations. Each of the data transmitting clocks WCK01 and WCK23 is provided as a differential signal pair. While a first data transmitting clock pair (WCK01, /WCK01) is connected to data input/output pins DQ0 through DQ7 and DQ16 through DQ23, a second data transmitting clock pair (WCK23, /WCK23) is connected to data input/output pins DQ8 through DQ15 and DQ24 through DQ31.
As shown in FIG. 3, the data transmitting clock pairs (WCK01, /WCK01) and (WCK23, /WCK23) are interconnected through ball grid array (BGA) package balls in the first and second memory chips 120 and 130. In the first memory chip 120, the first data transmitting clock pair (WCK01, /WCK01) is respectively connected to a pin located in the 3rd column of B row (B3) and to a pin located in the 4th column of B row (B4), the second data transmitting clock pair (WCK23, /WCK23) is respectively connected to a pin located in the 9th column of B row (B9) and to a pin located in the 10th column of B row (B10), and a command and address transmit clock pair (CK, /CK) is respectively connected to a pin located in the 7th column of N row (N7) and to a pin located in the 7th column of P row (P7). The package of a second memory chip 130 is facing the package of a first memory chip 120 along the horizontal axis of the memory system in a mirroring scheme, and the first data transmitting clock pair (WCK01, /WCK01) in the second memory chip 130 is connected to pins located in B3 and B4, the second data transmitting clock pair (WCK23, /WCK23) is connected to pins located in B9 and B10, and the command and address transmit clock pair (CK, /CK) is connected to pins located in N7 and P7.
The first and the second data transmitting clock pairs (WCK01, /WCK01) and (WCK23, /WCK23), and the command and address transmitting clock pair (CK, /CK) are delivered through signal lines on top of the board 110 and connected to respective pins located in B3, B4, B9, B10, N7, and P7 in the first memory chip 120. The clocks WCK01, /WCK01, WCK23, /WCK23, CK, and /CK are delivered to the second memory chip 130 through electrodes 111, 112, 113, 114, 115, and 116 placed underneath the pins located in B3, B4, B9, B10, N7, and P7 in the first memory chip 120 and connected to the pins located in B3, B4, B9, B10, N7, and P7 in the second memory chip 130. Accordingly, the signal lines delivering the clocks WCK01, /WCK01, WCK23, /WCK23, CK, and /CK in the second memory chip 130 form a stub structure that receives the load of the two memory chips 120 and 130, which results in a decrease of the signal integrity.